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The next-generation processing technology called A16, corresponding to TSMC’s 1.6nm process, is viewed as the start of the “Angstrom era,” with expectations of notable gains in performance and energy efficiency versus the current 2nm generation.
TSMC is expected to begin mass production of the A16 from Q4 2026, though commercial products using the process are likely to arrive in 2027–2028, according to WCCTech.
Compared with the refined 2nm version (N2P), the A16 is expected to deliver an 8–10% performance increase at the same voltage, reduce power consumption by 15–20% at the same speed, and raise transistor density by about 10%.
Further ahead, the A13 process is slated to debut in 2029 and is expected to shrink chip area by about 6%. The change is aimed at optimizing fields such as high-performance computing (HPC), AI, and mobile devices.
Reducing chip area also means more chips can be produced per silicon wafer, which can lower the cost per unit.
The article notes that the most advanced technology today—the 2nm generation—has begun commercialization on smartphones since the start of this year.
In particular, leading devices include the Samsung Galaxy S26 and Samsung Galaxy S26+. In markets such as Europe, South Korea, India, Southeast Asia, the Middle East and Africa, the two models use the Exynos 2600, a chip designed and manufactured by Samsung through Samsung Foundry on the company’s 2nm process.
On the Apple side, the iPhone 17 Pro Max uses the A19 Pro chip manufactured by TSMC on the 3nm generation third (N3P) process.
As process size shrinks, transistors become smaller, enabling more transistors to be integrated on the same area. Higher transistor density shortens the distance electrons travel, which can improve clock speed and processing performance while reducing energy consumption for each transistor on/off transition.
In addition to shrinking size, TSMC’s 2nm chips use the Gate-All-Around (GAA) architecture. In GAA, the channel is surrounded on all four sides rather than three as in the earlier FinFET technology. The approach is described as reducing leakage, improving current control, and allowing transistors to switch faster, supporting both stronger performance and improved power efficiency.
The article says TSMC’s Angstrom-era A-series roadmap includes A16, A14, A13, and A12, with A16 marking a major shift through backside power delivery technology called Super Power Rail (SPR).
In traditional designs, signal and power lines are placed on the front side of the silicon wafer. With SPR, they are moved to the backside and connected directly to the transistor’s source and drain terminals. This is expected to eliminate the need for signals to traverse dozens of intermediate metal layers, reducing resistance and voltage drop.
By freeing the front side for signal routing, the design can arrange signals more densely, increasing transistor density without further shrinking the process. Shorter, more direct electrical paths are also expected to reduce energy losses as heat, enabling faster transistor switching—particularly beneficial for heavy AI workloads.
The article adds that Intel and Samsung are pursuing similar backside-power approaches, with Intel naming its technology PowerVia.
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