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According to Counterpoint Research’s global semiconductor foundry market supply report, the market in 2025 is expected to reach record revenue of $320 billion, up 16% from the previous year. TSMC, with revenue growth of 36%, is forecast to capture 38% of the market share, while revenues of other companies rise by about 8%.
The widening gap is not expected to be temporary. Counterpoint attributes it to TSMC’s focus on advanced chip manufacturing, the ongoing rise in wafer prices, and expansion of advanced packaging technology.
Financial data indicate TSMC is concentrating on AI and high-performance computing (HPC) chip manufacturing processes. In Q4 2025, processes at 7nm and below contributed 74% of wafer revenue, with 3nm accounting for 24% and 5nm for 36%.
For the full year, the share of 3nm increased from 18% in 2024 to 24%, while 5nm remained roughly flat at around 36%. TSMC’s growth is supported not only by output but also by selling prices. The wafer average selling price (ASP) increased by about 15.9% per year during 2019–2025.
In 2025 alone, gross profit per wafer rose by about 3.3x, as price increases outpaced production costs.
TrendForce reports that TSMC has notified customers of price increases of 5–10% for 5nm and below lines from January 2026, including 2nm, 3nm, 4nm and 5nm. It also forecasts that 3nm process pricing will continue rising, with double-digit gains in the coming years.
Tom’s Hardware notes that TSMC can sustain pricing power because customers have limited alternatives at comparable scale and performance. For example, Samsung Electronics’ output at sub-5nm processes is still not sufficient to meet large orders.
Intel, despite pushing its foundry business, holds about 6% of the market share. It reported $4.5 billion in revenue in Q4 2025, but remains loss-making.
As long as no competitor can offer advanced chip manufacturing at scale with comparable performance, TSMC retains pricing power. The report states that each step increase in output translates almost directly into outsized revenue growth.
TSMC is also expanding advanced packaging, creating a second revenue stream. CoWoS capacity (TSMC’s 2.5D advanced packaging technology) doubled from about 35,000 wafers per month at the end of 2024 to around 80,000 by the end of 2025. The next target is about 130,000 wafers per month by the end of this year.
Counterpoint Research’s Foundry 2.0 classification indicates that the OSAT segment (outsourced packaging and testing) grew by about 10% in 2025. Companies such as ASE Technology Holding (including SPIL) and Amkor Technology mainly absorb demand beyond TSMC’s internal capacity.
While OSAT companies typically handle lower-margin steps, key steps such as fabricating silicon interposers and the chip-on-wafer process in early stages remain performed by TSMC. Substrate assembly and testing, which have lower margins, are increasingly outsourced.
Counterpoint forecasts that total advanced packaging capacity across the industry could rise by about 80% in 2026, with TSMC’s CoWoS expansion absorbing most of this increase.
At the same time, competitive efforts are ongoing. Samsung Electronics is accelerating its 2nm program and could begin taking external customers if yield improves. Intel has introduced its first products using the 18A process into Panther Lake and Clearwater Forest lines, though initial output remains limited. Chinese chipmakers are also expected to sustain double-digit growth supported by large-scale domesticization programs.
In the near term, at least through this year, no company is expected to close the gap with TSMC. Its 38% market share reflects long-term accumulation of core advantages in technology, pricing power, and vertical integration, and the report suggests rivals would need many years to catch up even if they accelerate.
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